Increased performance, both with regard to more complex functionality and higher speeds, is generally the goal of efforts in advancing the semiconductor arts. One method that has been used for achieving this goal is scaling downward the size of transistors used in advanced semiconductor devices. However, as devices have become smaller, such scaling has become problematic due to short channel effects, insufficient drive voltages and inadequate sub-threshold performance. Thus to continue to increase or enhance device performance, particularly transistor device structures, it would be desirable to create transistor device structures that overcome or reduce the above mentioned problems.
One such transistor structure that theoretically offers advantages that overcome the aforementioned problems of scaling device size downward is the dual-gated transistor structure. However, such transistors have proven difficult to fabricate, making it difficult to take advantage of increased drive current and sub-threshold performance. This difficulty is the result of the absence of a technique or method for accurately aligning the front and back gate structures to one another. As a result of this deficiency, alternate transistor structures that do not offer all of the advantages of dual-gate transistors have been pursued. Exemplary of such alternate structures are “surround gate” and “DELTA” gate transistors. However, while such alternate devices provide some of the benefit predicted for dual-gated transistors, these partial benefits are only realized at the expense of difficult manufacturing processes that result in an integrated circuit having highly irregular surface topology due to the vertical nature of such alternate devices.
It would therefore be advantageous to have methods for forming dual-gated transistor devices that employ straightforward semiconductor fabrication methods. It would also be advantageous if such methods would be useful to form dual-gated transistors that have an essentially standard transistor surface profile, thus avoiding the problematic highly irregular surface topology of the aforementioned alternate devices. In addition, it would be advantageous if such methods could be employed to form such dual-gated transistor devices having high drive current and superior sub-threshold performance.